The present invention relates to a MNOS memory transistor and particularly to such a transistor which can be written solely using avalanche injection.
MNOS memory transistors using silicon nitridesilicon oxide double dielectric between the channel region and a conductive gate have been proposed, wherein electrons are tunnel injected into the interface between the silicon nitride and silicon dioxide, as described by Wallmark and Scott in the article, "Switching and Storage Characteristics of MOS Memory Transistors," RCA Review, Vol. 30, page 335 (1969). However, to achieve tunnel injection of the electrons in such a transistor requires a very thin (less than 50 A) silicon oxide layer, which is difficult to control and reproduce in a production environment.
Another type of memory transistor is the floating gate transistor such as shown in U.S. Pat. No. 3,660,819 to Frohman-Bentchkowsky, entitled FLOATING GATE TRANSISTOR AND METHOD FOR CHARGING AND DISCHARGING SAME, issued May 2, 1972. The floating gate transistor uses avalanche injection to store charge in a floating conductive gate. This type of transistor can use a thicker dielectric layer (500 A to 1000 A). However, since the gate must be maintained floating to store the charge, in the practical use of the transistor in a memory circuit a second gate must be provided over the floating gate to determine whether a charge is being stored in the floating gate. The need of a second gate makes the transistor more complex to manufacture.